{
  "abstract": "A bus controller-based programmable logic device (PLD) architecture is provided and includes a dual-port unit interposed between bus controllers. The dual port unit includes first and second data transfer layers. The first data transfer layer includes write and read areas for data transfer between the first and second bus controllers, respectively. A write to the read area is prevented during a read by the second bus controller. The second data transfer layer includes read and write areas for data transfer between the first and second bus controllers, respectively. A write to the read area is prevented during a read by the first bus controller.",
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  "title": "Non-standard bus controller-based programmable logic device (PLD) architecture for interconnecting multiple bus controllers and increased numbers of PLD modules",
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