OpenTechnical
This is a record of a document published elsewhere, first published by the United States Patent and Trademark Office, as US-12602023-B2, on 14 April 2026. OpenTechnical did not first disclose it. The identifier, hashes and timestamps below record what this library served and when, not when the material became public. View the original.

OT-2026-000000700

Non-standard bus controller-based programmable logic device (PLD) architecture for interconnecting multiple bus controllers and increased numbers of PLD modules

Published
Permanent URL
Classification
Sensors, Controls & Machine Vision › Industrial Control
Original source
US-12602023-B2, the United States Patent and Trademark Office, 14 April 2026
Document SHA-256
5250a7a65a3f163703a62d1ae5c6cc1094c80bb775cacf4f9039884e1d46c28e

Abstract

A bus controller-based programmable logic device (PLD) architecture is provided and includes a dual-port unit interposed between bus controllers. The dual port unit includes first and second data transfer layers. The first data transfer layer includes write and read areas for data transfer between the first and second bus controllers, respectively. A write to the read area is prevented during a read by the second bus controller. The second data transfer layer includes read and write areas for data transfer between the first and second bus controllers, respectively. A write to the read area is prevented during a read by the first bus controller.

Publication information

Citation

OpenTechnical Publication OT-2026-000000700, “Non-standard bus controller-based programmable logic device (PLD) architecture for interconnecting multiple bus controllers and increased numbers of PLD modules,” published September 15, 2026 at 19:03:16 UTC, https://opentechnical.org/p/OT-2026-000000700.

To cite specific content, add the paragraph or figure numbers.

Terms

This record reproduces a document published elsewhere and is provided for reference and study. Rights in the original remain with its owner. See the publication policy.